[flotus1]

Epyc Milan still isn't available for single end-users, yet here are the first leaks for its successor.

https://wccftech.com/amd-epyc-genoa-...a-6096-socket/

The most interesting points:

• up to 96 cores
• 12 memory channels
• DDR5-5200
• new SP5 socket with 6096 pins
• 320W TDP, configurable up to 400W

Of course, none of these specs are confirmed. But I'm still excited

[gnwt4a]

u r giving publicity to a plagiarizing site that never gives credit to its sources. a decent site that gives full credit to its sources is this



https://videocardz.com/newz/amd-zen4...2-instructions


which mentions avx3-512, 5nm etc.
--

[flotus1]

I did not expect such strong feelings towards any of those news sites. I would have linked the original article, but that's from a german news outlet as far as I am aware of.
Since every source I found rehashes the same information, I just linked one of them at random.

[Malinator]

I agree, this leak is a hell of an appetizer
Just to reflect the implications of those rumoured characteristics for CFD:
Each memory channel with DDR5-5200 is able to provide roughly 2* of memory bandwidth compared to currently top-notch DDR4-3200 in EPYCs.
Now top it up with 12 vs current 8 memory channels per CPU (1.5* rise),
and one can vaguely estimate EPYC Genoa's to provide 3* (triple, for God's sake) growth in memory bandwidth.
Now, given the fact that performance in CFD apps on modern servers are in fact bound by memory bandwidth, this upgrade of memory subsystem may actually be game-changing. Of course, there are still a lot of questions regarding actual performance (for example, will IOD chiplet and Infinity fabric be able to keep up with such a bandwidth rise), but even a potential to obtain near-triple performance rise in one generation is mind-boggling. Exciting times ahead..

[danbence]

That is quite a jump in performance. I remember when 192 cores was a respectable sized cluster

[xuegy]

Honestly, I would say EPYC is trash for CFD users.

Currently I'm using PSC Bridges-2 (2x EPYC 7742, 128 cores.) The theoretical memory bandwidth is only 1.33x to Intel, but I have to pay 4x more SUs. And I'm suffering from SIGFPE error(no such bulls*** on Intel CPUs).

If you own a EPYC workstation it might be fine (just pick the cheapest one with 8 memory channels). But for HPC users please think twice, 128 cores will be a nightmare.

[flotus1]

Well, everyone is entitled to their own opinion. I can't comment on the cause of SIGFPE, obviously. But if you are paying for 64-core Epyc CPUs to run CFD workloads, you are probably doing it wrong.

[xuegy]

The issue is I don't have much choice. The HPC resource is free through XSEDE(if you have heard about it). I would prefer 16 core EPYC HPC systems but I don't think there's any.
The SIGFPE problem is caused by AOCC optimization. So it's pretty much a black box to me.

[Malinator]

Well, it looks like something huge is coming) Tomorrow AMD is going to host some kind of HPC-related announcement, and while the focus would likely be on Instinct accelerators that are of less interest to CFD community, thet most likely would be accompanied with new EPYC procs. Folks found out on that teaser picture https://twitter.com/LisaSu/status/1456604871524761609 that every socket for some EPYC proc on this motherboard comes with.. 16 DIMM slots (presumably DDR5, right? ). Soo.. can we expect to see in a few days (but not be able to put a hand on it for another year ) EPYCs with 16 channels of DDR5?
Well, to add a bit of pragmatism, it also can be just a regular Milan with standard 8ch/16 DIMMs for DDR4 just for huge amount of DRAM, but one can hope for the good, right? )

[flotus1]

The next CPU releases from AMD should still be based on Zen3. They are adding more L3 cache to existing CPUs. The initial batch should be 4 new Epyc CPUs, each with 512MB of additional L3 cache. https://www.servethehome.com/server-...b-onboard-era/
Current Zen3 desktop CPUs will get a similar treatment with more L3 cache stacked on top.
I somehow doubt that they will transition to 16 memory channels immediately with Epyc Genoa. The picture more likely shows a dual-socket server board with 2 slots per channel. 16 DDR5 memory channels would be a ton of additional pins. SP3 has around 4000 pins, and SP5 is rumored to have around 6000 pins. That's just not enough for 16 channels, without dropping most other I/O capabilities.

Edit: as expected, just a bunch of Zen3 Epycs with more L3 cache stacked on top, which won't be available for retail any time soon.

[aparangement]

12-channel ddr5 4800 is good improvement already, more than double bandwidth.

Intel plans to integrate HBM to next gen xeon, that should be a huge jump.

Originally Posted by flotus1

The next CPU releases from AMD should still be based on Zen3. They are adding more L3 cache to existing CPUs. The initial batch should be 4 new Epyc CPUs, each with 512MB of additional L3 cache. https://www.servethehome.com/server-...b-onboard-era/
Current Zen3 desktop CPUs will get a similar treatment with more L3 cache stacked on top.
I somehow doubt that they will transition to 16 memory channels immediately with Epyc Genoa. The picture more likely shows a dual-socket server board with 2 slots per channel. 16 DDR5 memory channels would be a ton of additional pins. SP3 has around 4000 pins, and SP5 is rumored to have around 6000 pins. That's just not enough for 16 channels, without dropping most other I/O capabilities.

Edit: as expected, just a bunch of Zen3 Epycs with more L3 cache stacked on top, which won't be available for retail any time soon.

[aparangement]

Originally Posted by xuegy

Honestly, I would say EPYC is trash for CFD users.

Currently I'm using PSC Bridges-2 (2x EPYC 7742, 128 cores.) The theoretical memory bandwidth is only 1.33x to Intel, but I have to pay 4x more SUs. And I'm suffering from SIGFPE error(no such bulls*** on Intel CPUs).

If you own a EPYC workstation it might be fine (just pick the cheapest one with 8 memory channels). But for HPC users please think twice, 128 cores will be a nightmare.

I think it's really difficult to find a intel based clould service that's designed for CFD now, almost all of them are using epyc. The performance advantage is just too huge.

For CFD typically there should be 32c/socket options.